Memory Layout Engineer At ARM In Noida

Location: Noida

Company: ARM

This opening is for a memory layout designer in our PHYSICAL IP – MEMORY group in Noida. We work on innovative memory architectures in pioneering technology nodes to enable the best Arm Systems in all the markets. This position is a rare opportunity for you as a memory layout professional to work with our successful layout and circuits team. You will be working on floor planning, metal planning, efficient layout techniques to extract the best PPA in groundbreaking process technologies.

Responsibilities

• Implementation of quality full-custom layouts of high-performance arrays and memory blocks from supplied schematics from planning stages through final layout verification and review, in accordance with strict guidelines for performance and manufacturability.
• Interpretation and implementation of all physical design rules in the most advanced manufacturing processes used by Arm.
• Custom layout and verification of complex memory cells.
• Physical design verification (DRC/LVS/DFM) resource for all types of circuit and test layouts using calibre verification tools.
• Electro-migration and IR checks for reliability and integrity.

Required Skills and Experience

• The ideal candidate is expected to have 2+ years relevant layout design experience with a Bachelor/Masters or equivalent education.
• Ability to understand, plan and organize work using complex schematics of hierarchically structured circuits.
• Understanding of layout techniques for optimization of power, speed, and area for data path, bitcell arrays, word line drivers, control blocks, and other complex memory circuits.
• Ability to quickly interpret and repair complicated LVS and DRC problems using innovative verification software.
• Must have experience with Cadence Virtuoso layout systems.
• Organized and exhibits attention to detail

“Nice To Have” Skills and Experience

• Understanding of layout techniques for design-for-manufacture in advanced (7nm/5nm/3nm/2nm) processes.
• Ability to identify possible design tradeoffs with circuit design leads, based upon assumptions, inherent knowledge, and design analysis.
• Programming experience Tcl, Perl, shell, Skill, Scheme.