Analog Layout Design Engineer At Synopsys In Bengaluru

Location: Bengaluru

Company: Synopsys

We are hiring self-motivated individual contributors for our next generation DDR/HBM/UCIe PHY IP’s!

Responsibilities

• Hands on in layout development of cutting edged technologies for next generation DDR/HBM/UCIe IP development
• Good problem-solving and debugging skills
• Work on layout floorplan, routing and physical verifications to meet quality requirements

Requirements

• Qualification: BTech/MTech
• Skills/Experience: 2+ years relevant
• Experienced in developing quality layout meeting timelines and verifications DRC, LVS, ERC, Antenna
• Good understanding of deep submicron effects, floorplan techniques in CMOS, FinFET, GAA process technologies 7nm and below
• Exposure to layout matching techniques, ESD, latch-up, EMIR, DFM, LEF generation
• Collaboration with teams, foster accountability and ownership
• Good written, verbal communication and interpersonal skills