Associate III – VLSI -Std cell Layout-SV At UST In Bengaluru

Location: Bengaluru

Company: UST

• Development of the standard cell library from scratch and support of existing libraries Characterization and views generation of the libraries with several custom PVT corners.
• Modeling of any new & existing cells to support Industry wide PnR, Simulation & Signoff tools.
• Maintain accurate and thorough documentation of work, design flows and reports.
• Experience in the field of Standard cell design, characterization, modelling and QA.
• Experience in advanced technology nodes, 28nm and below.
• Should be well versed with standard EDA tools used for RC-extraction, SPICE simulators and schematic/layout editors.
• Understanding issues related to advanced nanometer technologies, IR, electro migration, SI, LOD, Proximity-effects etc is a must.
• Good debugging and problem solving skills.
• Scripting skills in csh, perl or tcl is an added advantage.
• Should be a good team player. Basic knowledge of analog layout is needed.
• Knowledge of scripting languages (Perl, TCL, Skill, Ocean) is an added advantage

Skills

Standard cell layout,EDA,Layout