Lead Design Engineer At Cadence In Bengaluru and Hyderabad

Location: Bengaluru and Hyderabad

Company: Cadence

• Development, automation and maintenance of EDA flows and scripts for physical implementation
• Develop TFM to optimise PPA for IP’s and Soft Controllers
• PPA characterisation and optimisation of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
• Digital design implementation using Cadence EDA tools – Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools

Required skills

• Educational Qualification: MS/MTech/BE/ BTech  in Electronics from reputed institutes
• Physical design experience in ASIC design environment
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing, Timing Analysis, Power Analysis and Formal Verification
• Should have excellent leadership, communication, analytical and problem-solving skills
• Should be self-motivated and good team player